Offer information

Analog Design

Marvell Technology

Sector / reference area

Electronic

Carrying out the work activity

Pavia

Number of positions available

1

Type of contract

Fixed-term contract

Expected salary

25.000 euro anno

Description

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Central Engineering – Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro, and datacenters. We address the bandwidth, capacity, and power issues faced by cloud computing, mega data centers that power the social media giant platforms. Our innovative approaches have resulted in the company’s products being first to market in many of the key areas, developing the most advanced chips and subsystem solutions to address the ever-increasing demand for higher data rates driven by video-on-demand, gaming, and other real-time data streams. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity. As a member of a dynamic CE-OPHY team, the candidate will be responsible for designing circuits used for high-speed optical transceivers. The member will have an opportunity to work on a deep submicron process and collaborate with the team on next-gen high-speed optical transceivers.

What You Can Expect

• Join a growing team developing cutting-edge products for artificial intelligence and cloud data center applications.
• Work with the most advanced technology nodes: 3nm FinFET and 2nm GAAFET.
• Design integrated circuits for electrical and electro-optical interfaces operating at 100+ Gb/s.
• Gain hands-on experience with various CAD tools (primarily Cadence) to design and simulate high-performance analog circuits.
• Learn and apply advanced analog and high-speed layout techniques.
• Collaborate closely in a team-oriented environment to drive effective results.
• Location: Pavia, Italy.
• Work Model: Full-time, on-site.

 

What We’re Looking For

• BSc degree in Electronics Engineering (for the sponsorship of an industrial master thesis) OR currently working on your master’s or PhD thesis (for an extracurricular contract).
• Self-motivated, eager to learn new technologies, and able to work effectively within a team of talented individuals.
• Academic knowledge of CMOS analog design.
• Basic understanding of RF design techniques (a plus).
• Solid understanding of CMOS processes and fabrication.
• Basic knowledge of IC layout.
• Strong written and verbal communication skills.
• Proficiency in both spoken and written Italian and English (B2 level or higher).

Candidate requirements

BSc degree in Electronics Engineering (for the sponsorship of an industrial master thesis) OR currently working on your master's or PhD thesis (for an extracurricular contract). Self-motivated, eager to learn new technologies, and able to work effectively within a team of talented individuals. Academic knowledge of CMOS analog design. Basic understanding of RF design techniques (a plus). Solid understanding of CMOS processes and fabrication. Basic knowledge of IC layout. Strong written and verbal communication skills. Proficiency in both spoken and written Italian and English (B2 level or higher).

Planned activities

Join a growing team developing cutting-edge products for artificial intelligence and cloud data center applications. Work with the most advanced technology nodes: 3nm FinFET and 2nm GAAFET. Design integrated circuits for electrical and electro-optical interfaces operating at 100+ Gb/s. Gain hands-on experience with various CAD tools (primarily Cadence) to design and simulate high-performance analog circuits. Learn and apply advanced analog and high-speed layout techniques. Collaborate closely in a team-oriented environment to drive effective results.